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?2000 fairchild semiconductor international www.fairchildsemi.com rev. 1.0.0 february. 2000. 1 features ? commutation fg, pg is executed by 1-hall ? soft switching at output terminal reduces switching impulse. ? 3-phase full wave bldc motor driver. ? voltage reference (uses band gap circuit) ? built-in thermal shut-down (tsd) circuit description fan8402d is a bipolar integrated circuit used to drive 3- phase brushless dc motor in full wave mode using 1-hall sensor. fan8402d uses 1-hall for commutation and pg gen- eration. it is a special circuit for soft switching using 1-hall reduces the emi and eliminates snubber. the fg is gener- ated by bemf. 20-sop-300 typical applications ? video cassette recorder (vcr) cylinder (drum) motor ? other 3-phase bldc motor ordering information device package operating temp. fan8402d 20-sop-300 - 25 c ~ +75 c fan8402dtf 20-sop-300 - 25 c ~ +75 c fan8402d (KA3081D) 3-phase bldc motor driver
fan8402d (KA3081D) 2 pin assignments pin definitions pin number pin name pin function description 1v reg regurator output 2 c_dly pg. delay 3s_v cc signal v cc 4hall - hall- input 5 hall+ hall+ input 6 c_pk peak detector of hall signal 7 c_osc start-up oscillator 8p_v cc power v cc 9 u_out u-phase output 10 v_out v-phase output 11 w_out w-phase output 12 r nf output current sensing 13 ntl_in - input from the neutral point of the motor coils. 14 ntl_in+ input from the neutral point of the motor coils. 15 s_gnd signal ground 16 c nf phase compensation 17 fg_out fg. output 18 nc - 19 pg_out pg. output 20 v ctl output current control 12345678910 11 16 15 14 13 12 20 19 18 17 fan8402d v reg c_dly s_v cc hall - hall+ c_pk c_osc p_v cc u_out v_out v ctl pg_out nc fg_out c nf s_gnd ntl_in+ ntl_in - r nf w_out
fan8402d (KA3081D) 3 internal block diagram 15 1 54 3 6 7 17 19 2 13 14 8 9 10 11 12 20 16 + - + - + - + - + - bandgap & bias, tsd each blocks commutation logic & pre_drive power drive bemp comparator pg delay control pg, fg out peak detecter start_up osc commutation & pg , fg tim ing generator v ctl v nf c_dly r nf w_out p_v cc v_out u_out ntl_in - ntl_in+ c_osc c_pk s_v cc hall+ hall - v reg s_gnd pg_out fg_out
fan8402d (KA3081D) 4 equivalent circuit s description pin no. internal circuit hall input 5,4 output & current detection 9,10,11 8,12 fg output 17 pg output 19 4 5 v cc v cc v cc 8 9 10 11 12 15 p_vcc u_out v_out w_out r s (0.5 w ) 17 v cc v reg 19 v cc v reg
fan8402d (KA3081D) 5 equivalent circuits (continued) description pin no. internal circuit voltage control reference 20 19 v cc v cc
fan8402d (KA3081D) 6 absolute maximum ratings (ta=25 c) notes: 1. duty 1 / 100, pulse width 500 m s 2. 1) when mounted on glass epoxy pcb (76.2 114 1.57mm) 2) power dissipation reduces 9.6mw / c for using above ta=25 c. 3) do not exceed pd and soa(safe operating area). power dissipation curve recommened operating conditions (ta=25 c) parameter symbol value unit remark supply voltage (signal) v ccmax 20 v - maxium output current i omax 1.0 note1 a / phase regulator output current i regmax 10 ma power dissipation p d 1.0 note2 w no heat sink junction temperature t j 150 c- operating temperature t opr - 20 ~ +75 c ambient temperature (ta) storage temperature t stg - 40 ~ +155 c parameter symbol min. typ. max unit operating supply voltage(signal) s_v cc 4.5 5.0 5.5 v operating supply voltage(power) p_v cc 81218v 0 0 25 50 75 100 125 ta [ c] 150 175 1.0 no heat sink power dissipation(w) soa
fan8402d (KA3081D) 7 electrical characteristics (measured in test circuit, p_v cc =12v, ta=25 c) notes: the note in the chart means items calculated and approved in design not the items proven by actual test results. parameter symbol conditions min. typ. max. unit total supply volta g ev cc -8.0-18v supply current (1) i cc1 p_v cc =12v, v reg =open, v ctl =0v -11.217ma supply current (2) i cc2 p_v cc =12v, v reg =open, v ctl =0v -11.517ma regurator v reg output volta g e (2) v reg2 p_v cc =12v, i reg =0ma 4.7 5.0 5.3 v v reg output volta g e (5) v reg5 p_v cc =12v, i reg =10ma 4.7 5.0 5.3 v start-up oscillator c_osc operation frequency osc_ feq c_osc=47nf 6 8 10 hz c_osc char g in g current osc _ich c_osc=47nf - 0.5 - 2 - 3.5 m a c_osc dischar g in g current osc _idc c_osc=47nf 1 3 5 m a c_osc low threshold volta g eosc _thl c_osc=47nf 0.2 0.5 0.8 v c_osc hi g h threshold volta g eosc _thh c_osc=47nf 2.7 3.0 3.3 v voltage control v ctl start volta g ev ctl_st v ctl =0~2v when i o =25ma 1.01 1.26 1.51 v v ctl input volta g e ran g ev ctl_in v reg 0-v ref v v ctl input bias current v ctl_bi v ctl =2.0v - 1.0 1.5 m a gain gm r nf =0.47 w , v ctl =0~2v 0.38 0.45 0.52 a hall input input hall si g nal min. volta g e note v h_min 300 - - mvp-p pg hall 1st min. volta g e note v h_p1 60 - - mvo-p pg hall 2nd min. volta g e note v h_p2 55 - - mvo-p pg hall 3rd min. volta g e note v h_p3 75 - - mvo-p pg hall 1st-2nd level note d v h 5- -mvo-p fg (frequency generator), pg (phase generator) fg, pg hi g h level fg_pg _h - 4.5 - - v fg, pg low level fg_pg _l - - - 0.5 v 1st 2nd 3rd d vh
fan8402d (KA3081D) 8 electrical characteristics (continued) (measured in test circuit, p_v cc =12v, ta=25 c) notes: the note in the chart means items calculated and approved in design not the items proven by actual test results. parameter symbol conditions min. typ. max. unit tsd temp. threshold note tsd _t - 130 150 - c temp. hysteresis note tsd _h -2030- c output output saturation volta g e (upper) v su1 v ctl =4v, i o =600ma, r nf =0.47 w , r l =10 w -1.01.5v output saturation volta g e (under) v sd1 -0.40.7v ntl_in- input volta g e ran g ev ntl_in - -0-v cc v c nf volta g ev cnf v ctl =2v 1 - - v c_pk frequency cpk _frq c_pk=100 w + 0.1 m f 0.8 1 1.2 khz c_ck volta g e level cpk _v c_pk=100 w + 0.1 m f hall - =0.25v 0.4 - - vp-p c_dly c_dly char g in g current i c_dly c_dly=4nf -20 -30 -40 m a
fan8402d (KA3081D) 9 application information 1. system block diagram the figure 1 shows concept of soft switching for 3-phase output with a hall sensor. figure 1. ? peak detector generates clock pulses at the peak points of the hall signal. ? stair wave generator generates 3 stair wave signals 120 degree apart from the clock pulses. ? 3-phase motor drive circuit controls output currents to operate 3-phase motor using the vol ? tage difference between the 3 stair wave signals and fg hall signal. 2. structure of bldc motor consists of main and sub magnets. for every main magnet there are 3 submagnets as shown in fig 2. sub-magnet takes hall signal and goes through 6 gradual filtering steps purifying in order to operate 3-phase motor with one hall sensor. figure 2. peak detector stair wave generator 3-phase hall motor drive circuit hall signal u_output v_output 3-phase motor w_output u_stair v_stair w_stair common signal main-magnet sub-magnet hall output waveform (sub-magnet) n s n s n s n s n s n s n s n s
fan8402d (KA3081D) 10 3. principle of operation input circuit of 3-phase motor drive with soft-switching function is shown as the figure 3. figure 3. next the figure 4 shows common signal (hall signal) and each individual stairwave at its own position. figure 4. figure 5 shows hall signal and stairwave signal position. the section where the difference between hall signal and stairwave is within 100mv. hall - : hall common signal taken from sub-magnet. hall+: stairwave signal with 120 degree wave angle difference from one signal. i c1 i c2 i c3 i c4 i c5 i c6 q1 q2 q3 q4 q5 q6 hall+ hall - v-stair wave w-stair wave i ee i ee i ee u-stair wave common signal 1 hall signal u-stair wave w-stair wave v-stair wave
fan8402d (KA3081D) 11 figure 5. 4. peak detector hall signals and stairwave signals made from peak detectorss output rotate the motor. the peak detector circuit is shown in fig 6. figure 6. v abs in the figure 6 is a signal from twice amplified hall signal and hall bias at 2.5 volt as standard voltage as you see in the figure 7. region a rigion b 100mv (a) the difference between 1 hall signal and u-stair wave (b) the difference between 1 hall signal and v-stair wave (c) the difference between 1 hall signal and w-stair wave + - + - + - v abs amp v ref ck_zero v a comp2 v y v ref d1 d2 ck_peak c_pk r l c comp1
fan8402d (KA3081D) 12 figure 7. 5. drive output figure 8. the figure 8 shows the 3-phases of the bldc motor. the upper power trs in output group operate in linear area and the lower group work in saturation area. hall signal v abs v a ck_zero ck_peak 2v be hall bias index point v y u-upper u-lower v cc v-upper v-lower w-upper w-lower u v w r nf
fan8402d (KA3081D) 13 6. voltage control & current sensing figure 9. the circuit in the figure 9 outputs i ctl current when v ctl (control voltage from servo) is larger than the value of v ref . the v-i characteristic of this circuit is shown in the figure 10. figure 10. the cs-amp terminal amplifies by getting inputs from output terminal getting i ctl and r nf voltages. r nf resistance feedbacks the current in output terminal. + - 12 output drive 20 gain ctl i cs r nf v ctl v ref (4.95v) v ctl i ctl cs_amp + - i ctl a v ref v ctl a : slop i ctl v ctl ------------- 93u a v () ==
fan8402d (KA3081D) 14 timing chart h+ fg_out(2xbemp) peak detector out pg & output reset bemp comp.out commutation clock u-phase output current v-phase output current w-phase output current n s n s n s 123456123456123456
fan8402d (KA3081D) 15 test circuits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sw1 1 2 i reg = - 10ma 6nf sw2 sw3 hall signal generator 3k w 100 w 3k w sw5 1 2 47nf 100 w sw6 sw7 sw8 10 w (10w) 5 w (10w) 10 w (20w) 5 w (10w) ru1 ru2 rv1 rv2 v com sw9 sw10 10 w (10w) 5 w (20w) 0.47 w (20w) v cc 0.1 m f 2 1 rw1 rw2 sw11 - 90 shift circuit 10k w 10k w sw12 0.1 m f v reg c_dly s_v cc v ctl pg_out nc hall - fg_out hall+ c nf c_pk s_gnd c_osc ntl_in+ p_v cc ntl_in - u_out r nf v_out w_out f a n 8 4 0 2 d
fan8402d (KA3081D) 16 typical application circuits 3 4 5 1 15 16 20 12 11 10 9 8 14 13 2 17 17 7 6 s_v cc hall hall+ hall - 470 w c_pk 100 w 0.1 m f 47 m f c_osc peak detector start_up osc commutation fg, pg timing generator pg, fg out pg delay control bemf comparator fg_out pg_out c_dly 10nf ntl_in - ntl_in+ p_v cc u_out v_out w_out power drive r nf 0.47 w v ctl c nf - + s_gnd v reg 0.1 m f bangap & bias, tsd + - + - + - commutation logic & pre_drive each blocks v cc 10k w 1 m f
20-sop-300 0.60 0.20 0.024 0.008 #1 #10 #11 #20 13.70 0.20 0.539 0.008 1.27 0.050 7.62 0.300 1.70 0.10 0.067 0.004 0.05 0.002 7.80 0.30 0.307 0.012 5.40 0.20 0.213 0.008 14.10 0.555 max 0~8 1.14 0.045 () 2.00 0.079 max0.10 max0.004 max min + 0.10 -0.05 0.20 + 0.004 -0.002 0.008 + 0.10 -0.05 0.40 + 0.004 -0.002 0.016
trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification p roduct status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. qfet? qs? qt optoelectronics? quiet series? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? uhc? fastr? globaloptoisolator? gto? hisec? isoplanar? microwire? optologic? optoplanar? pop? powertrench ? rev. f1 acex? bottomless? coolfet? crossvolt? dome? e 2 cmos tm ensigna tm fact? fact quiet series? fast ? vcx?

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